1. Field of the Invention
The invention relates to nonvolatile memory, and particularly a non-volatile memory structure with a program element at least partially formed in a polysilicon layer, optimized for particular applications such as programmable logic devices.
2. Description of the Related Art
Non-volatile memory devices of the type commonly referred to in the art as EPROM, EEPROM, or Flash EEPROM serve a variety of purposes, and are hence provided in a variety of architectures and circuit structures. One such application is termed a "programmable logic device" or PLD. The PLD includes a programmable array of non-volatile memory devices which can be customized by end users for particular applications.
As with many types of integrated circuit devices, some of the main objectives of non-volatile memory device designers are to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. Cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry. EEPROM devices are one such device that must meet these challenges. In some applications, such as flash memory cards, density is at a premium, while in applications such as programmable logic devices (PLD's), speed is more important and space is at less of a premium.
EEPROMS (electrically erasable/programmable read-only memories) generally employ Fowler-Nordheim (F-N) tunneling for both programming and erasing. The term "flash", when used with "EEPROM", generally refers to a device programmed by hot electron injection. Typically, flash technology employs a floating gate structure with a thin oxide layer between the floating gate and the drain side of the transistor where Fowler-Nordheim tunneling occurs.
As process technology moves toward the so-called 0.18 and 0.13 micron processes, the conventional "stacked gate" EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In addition, designers are driven to reduce the power requirements of such devices as a result of such sealing. In non-volatile memory devices, the program and erase functions generally require the largest voltages and consequently reducing program voltages achieves overall device power savings.
An alternative to the aforementioned FN tunneling-based EEPROM cell structure is presented in Ranaweera, et al., "Performance Limitations of a Flash EEPROM Cell, Programmed With Zener Induced Hot Electrons," University of Toronto Department of Electrical Engineering (1997). Discussed therein is a flash EEPROM cell which accomplishes programming by establishing a reverse breakdown condition at the drain/substrate junction, generating hot electrons which are then swept onto to the floating gate to program the cell.
FIGS. 1A, 1B and 1C of Ranaweera, et al. are reproduced as FIGS. 1A, 1B and 1C of the present application. FIGS. 1B and 1C show cross-sections of the cell shown in FIG. 1A. As shown in FIG. 1C, a "ZEEPROM" cell comprises a source and drain region, floating gate and control gate, with a P+ pocket implant extending part way across the width of the drain region to generate hot electrons for programming. The flash ZEEPROM cells are fabricated using CMOS compatible process technology, with the addition of a heavily doped boron implant for the P+ region replacing the LDD region. A sidewall spacer is necessary to form the self-aligned N+ source and drain regions and to avoid counter-doping of the P+ pocket.
To program the flash ZEEPROM cell, the P+N+ junction is reverse-biased to create an electric field of approximately 10.sup.6 volt/cm. and generate energetic hot electrons independent of the channel length. The P+ region adjacent to the drain enhances this generation. A low junction breakdown current can be used for programming by optimizing the P+ N+ junction depth and controlling the applied drain voltage. One disadvantage of this cell is that a low drain voltage (approximately one volt) must be used to read the cell since the P+ region exhibits a low breakdown voltage which can contribute to "soft programming." Another disadvantage is that the cell provides lower read current compared with conventional flash memory cells since the P+N+ heavy doping required for breakdown reduction allows for very little channel conduction in that portion of the channel. Further, the P+N+ doping increases cell capacitance in the read path and increases switching delays. Erasing in the cell is performed by Fowler-Nordheim tunneling of electrons from the floating gate to the source region using a negative gate voltage and a positive supply voltage connected to the source similar to conventional flash EEPROM cells.
Another alternative cell structure using hot election programming generated by a reverse breakdown condition at the drain is described in the context of a method for bulk charging and discharging of an array of flash EEPROM memory cells in U.S. Pat. No. 5,491,657 issued to Haddad, et al., assigned to the assignee of the present invention. In Haddad, et al., a cell structure similar to that shown in cross-section in FIG. 1B of the present application may be used, as well as a substrate-biased p-well in n-well embodiment. In the first embodiment, an N+ source region includes an N+ implant region and an N diffusion region, and the erase operation (removing electrons) is accomplished by applying (-)8.5 volts to the control gate for 100 milliseconds, and (+)5 volts to the source for 100 milliseconds, with the drain being allowed to float. In contrast, programming (adding electrons to the gate) is achieved by applying a negative 8.5 volt to the substrate for 5 microseconds, zero volts to the drain and control gate with the source floating. The bulk charging operation can just as easily be done on the source side rather than the drain side in a case where the cell is provided in a P well by applying -8.5 volts to the P well for 5 microseconds, 0 volts to the source and control gate with the drain being allowed to float.
Yet another structure and method for programming a cell is detailed in co-pending U.S. patent application Pat. No. 5,978,272, inventors Hao Fang, et al., filed Jul. 24, 1998 and assigned to the assignee of the present application. FIGS. 1A and 1B of the Fang, et al. application are reproduced herein as FIGS. 2A and 2B, and FIGS. 2A and 2B of the Fang application are reproduced as FIGS. 3A and 3B of the present application. The Fang, et al. application uses the programming method disclosed in Haddad, et al. to form a high density, low program/erase voltage and current, and fast byte programming and bulk erase and fast reading speed non-volatile memory structure specifically designed for programmable logic circuit applications.
In Fang, et al. the non-volatile memory cell 10 in FIGS. 2A, 2B is formed of a P substrate 12 having embedded therein an N+ source region 14, an N-type diffused drain region 16, a floating gate 18 capacitively coupled to the P substrate 12 through a tunnel oxide 20, or other gate dielectric such as nitride oxide; and a control gate 22 capacitively coupled to the floating gate 18 through an oxide/nitride/oxide, or other type of inter polysilicon dielectric, film 24,26. Diffused region 16 is formed of a shallowly diffused but heavily doped N-type junction, while source region 14 is formed of a deeply diffused but lightly doped N junction. The relatively thin gate dielectric 20 (an oxide of 60 to 150 .ANG. in thickness) is interposed between top surface of substrate 12 and conductor polysilicon floating gate 18. Control gate 22 is supported above the floating gate by the inter-poly dielectric layer 24,26. Avalanche program and erase bias configurations of the memory cell of the Fang, et al. application are shown in FIGS. 3A and 3B, respectively.
Program and erase operations are illustrated in FIGS. 3A and 3B. To program the cell, electron injection is effected from the drain side. In this case, programming operation is accomplished by applying +3 volts on the drain and -6 volts on the P substrate so as to shift upwardly the threshold voltage V.sub.t by 4 volts in approximately 0.002 seconds. To erase, holes are injected from the drain side by applying +6.5 volts on the drain and -3 volts on the P substrate so as to shift down with the voltage threshold V.sub.t by 4 volts. Utilizing the substrate bias configuration suppresses hot hole injection due to the fact that the location of the high field is away from the oxide interface, the magnitude of the maximum field strength is reduced by more than 50%, and the vertical field does not favor hole injection.
FIGS. 4A and 4B show FIGS. 10A and 10B of the Fang, et al. application which teach a single polysilicon layer embodiment of the Fang, et al. cell. In such an embodiment, the control gate is replaced with a diffusion region. The control gate can be switched between 0 volts and V.sub.cc to select and de-select the cell during the read period and between V.sub.jb and 0 volts to program and erase the cells as set forth above. A select transistor is added at the source side to enable a fast read of the memory cell. In this operation, the gate of the added select transistor is set at less than or equal to zero volts during program and erasing and at V.sub.cc with V.sub.d less than or equal to V.sub.cc and V.sub.dm =0 volts via turning on the memory cell for the read period. (V.sub.d is the drain voltage for the select transistor and V.sub.dm is the drain voltage for the memory transistor.) Cell size is decreased in comparison to conventional single poly memory cells for programmable logic devices. The bias configurations for the single poly memory cell are disclosed in FIG. 4B.
Generally, arrays of such individual memory cells are formed on a single substrate and combined with sense and read circuitry, and connected by row-wise and column-wise conductive regions or metallic conductors to allow for array wide bulk program and erase as well as selected bit programming.
In the aforementioned prior art references, each of the devices is provided as an NMOS transistor in a P-doped substrate. The only exception is the Haddad et al reference wherein an NMOS transistor is formed in a p-well which itself is formed in an n-well in a p-type substrate.
Each of the aforementioned configurations presents advantages and disadvantages in use in particular applications. Nevertheless, improvements in both the structure of individual cells and the manner in which they are connected together will result in more reliable, stable, faster, and lower power devices which can be programmed and erased at lower voltages.
Alternative cell constructions, saving space and increasing device efficiency, are generally desired.